A cache is a relatively high-speed, small, local memory which is used to provide a local storage for frequently accessed memory locations of a larger, relatively slow, main memory. By storing the information or a copy of the information locally, the cache is able to respond to memory references and handle them directly without transferring the request to the main memory. The result is lower traffic on the memory bus.
The most powerful microprocessors used in IBM compatible personal computers use a cache to satisfy the increasing demands of application programs for more memory and faster operating speeds. The microprocessors have a central processing unit (CPU) and an internal cache integrated on a single chip. The purpose of the internal cache is to reduce the number of times the CPU has to interface with external memory subsystems for its instructions and data. This is accomplished as follows. When the CPU requests data, the address of the data is examined by the internal cache to see if the data is in the cache. If the data (or instruction) is in the internal cache, the CPU request can be satisfied within about 15 ns as compared to 70 to 100 ns when the data or instruction is not in the internal cache.
In order to further reduce the access time when the data/instruction is not in the internal cache, a second-level cache is often placed on the bus connecting the CPU to the main memory, resulting in much faster access times than the main memory. Such a cache is described in copending Ser. No. 07/618,708 which provides a cache controller which sits in parallel with the main memory bus so as not to impede system response in the event of a cache miss. The cache controller includes tag and valid-bit storage for associatively searching the directory for cache data-array addresses. This configuration has the advantage that both the second-level cache and the main memory can simultaneously begin to look up the access address. In the event of a cache hit, the data/instruction is supplied by the cache with zero wait-state. In the event of a cache-miss, the parallel look-up technique incurs no additional penalty. This configuration also has the advantage that it is easy to use, it is software transparent, can be installed by the end user, and provides write-through memory update using the same timing as the CPU. However, since it uses the main memory bus, the bus itself is not optimized for cache accesses, resulting in a performance penalty.
It is therefore an object of the present invention to provide a bus between a cache and a microprocessor that is optimized for cache memory bandwidth.